Micron rejects 4F² memory-cell design over cost and density concerns
After two decades of evaluation, Micron plans to keep shrinking conventional memory cells before eventually moving to vertically stacked DRAM.
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After two decades of evaluation, Micron plans to keep shrinking conventional memory cells before eventually moving to vertically stacked DRAM.
Micron has rejected 4F² DRAM after roughly two decades of evaluation. It says the design adds manufacturing complexity and cost without worthwhile gains in how much memory fits on a chip, so it plans to keep shrinking conventional 6F² cells instead. Tom’s Hardware detailed the decision on 22 October.
Micron’s route beyond 4F² is now more specific: it plans to bond wafers in a later manufacturing process, use finer chip-patterning technology in subsequent generations and develop memory stacks that sit above processors. Tom’s Hardware set out those plans on 26 October. They describe technologies under development, not memory products already available.
Micron plans to introduce wafer bonding with its 1ε DRAM manufacturing process, which is under development and follows 1δ. Bonding joins wafer surfaces, but Micron has not said how it will use the method or what improvement it expects. For later generations, it plans High-NA EUV—a method of patterning finer features on chips—and new materials to keep shrinking memory cells.
Micron is also developing vertical high-bandwidth memory (vHBM) for stacks directly above processors used for superintelligence (SI), rather than beside them. Shorter connections are expected to reduce the time needed to move data and increase how much data can move at once. But putting memory over a processor makes cooling harder and limits how many stacks will fit. Micron expects vHBM to supplement conventional high-bandwidth memory, which it expects to supply most memory capacity in many SI accelerators.
A second design, vertical edge inference memory (vEIM), targets energy efficiency for processors in power-constrained devices such as autonomous vehicles and robots. Micron is developing structures to spread heat through its vertical memory stacks. It has not given commercial production dates for vHBM or vEIM.
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DRAM means dynamic random-access memory. The labels 4F² and 6F² describe cell area relative to the smallest feature size used to pattern a chip. At the same feature size, a 4F² cell would theoretically occupy about 33% less area than a 6F² cell. That could allow 50% more cells on a wafer—the disc on which chips are made—and potentially lower manufacturing cost per bit.
Scott DeBoer, Micron’s president and chief technology and products officer at its October 2026 event, said the charge-storing capacitors and the spacing between them determine how tightly memory cells fit. Making the underlying transistor smaller does not necessarily shrink the complete cell. Micron has built experimental 4F² devices, but DeBoer said the design faces physical limits as dimensions shrink further; he did not identify those limits. Samsung and SK hynix still included 4F² cells in their development roadmaps, according to TechInsights as cited by Tom’s Hardware. Those roadmaps do not establish commercial shipments.
Micron plans to increase the density of conventional DRAM by reducing the spacing between capacitors and shrinking manufacturing dimensions. Its 1δ process is scheduled for volume production in the second half of 2027. The company projects a bit-density gain in the mid-20% range over the preceding process.
Separately, Micron is developing multiple generations of 3D DRAM, which would stack memory cells vertically instead of relying only on making them narrower. DeBoer described it as a parallel path. Micron has not disclosed its architecture or a commercial launch schedule and says it will make the transition when manufacturing cost, complexity and device performance justify it.
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Update ·
Adds Micron’s plans for wafer bonding, finer chip patterning and memory stacks above processors, including their cooling and capacity constraints.